Careers

CURRENT OPENINGS

1) Lead Physical Design Engineer :

Designation: Lead PD Engineer
Experience: 7+ years
Location: Hyderabad/Bangalore  
Qualification: B.E / B.Tech/M.Tech

Responsibilities Include, But Not Limited To

  • Hands-on technical ownership of SoC for top-down/bottom-up physical design integration
  • Drive Sub-block/partition decisions, floorplan for the best PPAS
  • Generate sub-block/partition interface budgets, review
  • Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
  • Proficient in package co-design concepts
  • Implement timing and functional ECOs
  • P&R, Extraction, Physical verification, work towards STA closure
  • Build automation flows wherever needed/adapt to existing flows for re-use
  • Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
  • Needs to be automation savvy with high expertise in one of the programming languages used in the industry
  • Clearly know requisites for executing his/her job and lead by example
  • Bring tangible improvement in TAT with better quality
  • Mentor junior engineers

Minimum Qualifications:

  • A deep understanding of backend digital design flow, even to build a flow
  • Proficient in timing constraints, physical constraints
  • Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
  • Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/ICC2/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
  • Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is strongly preferred
  • Must possess excellent debug skills, analytical skills and the ability to work independently.
  • Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Preferred Skills:

  • Strong interpersonal skills both written and verbal
  • You are ambitious, goal-oriented, and dedicated
  • Collaborate effectively in a dynamic environment

2) Senior Physical Design Engineer:

Designation: Sr.Engineer
Experience: 4-7 years
Location: Hyderabad/Bangalore  
Qualification: B.E / B.Tech/M.Tech

Desired Skills :

  • Solid understanding and working knowledge of the SOC design with solid experience in taping out designs
  • Experience with 16nm finfet or smaller process nodes is strongly preferred
  • Hands-on experience with synthesis, floor-planning, block and full chip implementation with the latest industry P&R/STA flows and tools
  • Solid hands on experience with clock tree synthesis (CTS), multi-voltage, multi-clock designs and low power design
  • Strong working knowledge of Formal Equivalency Checks, LP checks, timing constraints generation and debug, UPF
  • Experience in block level floor-planning, implementing power grid and area/congestion optimization
  • Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage
  • Implement timing and functional ECOs
  • P&R, Extraction, Physical verification, work towards STA closure
  • Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/ICC2/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
  • Clearly know requisites for executing his/her job and lead by example
  • Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is strongly preferred
  • Strong interpersonal skills both written and verbal

3) Senior Physical Verification Engineer:

Designation: Sr. PV Engineer/Lead PV Engineer
Experience: 4+ years
Location: Hyderabad/Bangalore
Qualification: B.E / B.Tech/M.Tech

Desired Skills :

  • Mandatory Skills:  P&R from Netlist to GDS and physical verification using Synopsys ICV/Mentor Calibre working on cutting edge Technologies: 10nm, 14nm, 28nm
  • Responsible for run, debug and improve Cell/Block/Chip level PDV flows.
  • Responsible for physical verification of an SOC & closing on the PDV/LV Flows of the partition blocks
  • Performing various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level
  • Working with the Implementation team during the entire chip design cycle to drive signoff closure for tapeout
  • Strong knowledge of physical verification flows and methodology.
  • Knowledge of all aspects of ASIC physical design.
  • Real chip tapeout experience with a track record of successful signoff.
  • Layout design background and experience a plus.
  • Strong scripting skills using Perl, TCL, other scripting languages to debug flow related issues and make enhancements as appropriate.
  • Excellent verbal and written communication skills are required.
  • Excellent interpersonal and analytical skills with the ability to work independently.

4) STA Engineer

Designation: STA – Sr.Engineer/Lead
Experience: 4+ years
Location: Hyderabad/Bangalore  
Qualification: B.E / B.Tech/M.Tech

Desired Skills :

  • Experience in synthesis of complex SoCs block/top level and writing timing constraints
  • Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints
  • Experience in post-layout STA closure and timing ECOs
  • Worked in technology nodes 45nm and below
  • Experience in handling Low-power designs
  • Tools: Genus/Design Compiler, LEC, CLP, Tempus/PTSI/GT.
  • Experience in handling lower tech nodes that include 40nm,28nm,etc
  • Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC2 or Innovus.
  • Must have the ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time
  • Must possess excellent scripting skills – TCL or Perl
  • Experience in Synthesis and Formal is a plus
  • Excellent verbal and written communication skills are required.
  • Must possess excellent debug skills, analytical skills and the ability to work independently.
  • Must be highly motivated and  possess excellent team spirit.

5) DFT Design Engineers

Designation: DFT- Sr. Engineer/Lead
Experience: 4+years
Location: Hyderabad/Bangalore
Qualification: B.E / B.Tech/M.Tech 

Desired Skills :

  • He will be responsible for Designing and Implementing DFT techniques.
  • (Memory BIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/Logic BIST) on complex SOCs to improve testability.
  • Test Modes implementation and verification, scan insertion including on-chip compression..
  • Implementing, integrating and verifying memory BIST and boundary scan.
  • Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF).
  • Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution.
  • Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability. Mentoring new team member.
  • We are looking for a candidate with these specific personal characteristic and qualifications.

6) Senior RTL/ ASIC/ SOC Design Engineer:

Designation: RTL- Sr. Engineer/Lead
Experience: 5+years
Location: Hyderabad/Bangalore
Qualification: B.E / B.Tech/M.Tech 

Desired Skills :

  • Strong knowledge in IP/SOC design methodologies.
  • Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows
  • Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog
  • The design engineer should architect digital subsystem together with system designer
  • IP development and coding using standard coding guide lines
  • Working knowledge on code coverage, functional coverage, Lint, CDC etc
  • Experience with synthesis, STA, formality, ECO process, tool flows and scripting
  • Low power design
  • Knowledge in one or more of the following areas, a definite plus
    PCIe (protocol design, link layer, integration of PHY layer)
    Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer)
    Computer architecture/Processor fundamentals
    • knowledge of AMBA AHB/AXI protocol
    • Video/Audio Codecs knowledge is an added advantage
  • Excellent communication skills. Must be able to participate in global meetings
  • Mentoring juniors and enhancing their skill set

7) SOC/IP Design Verification Engineer:

Designation: Design Verification – Sr. Engineer/Lead
Experience: 5+years
Location: Hyderabad/Bangalore
Qualification: B.E / B.Tech/M.Tech 

Desired Skills :

  • Design and develop test benches using HVLs like System Verilog 
  • Deep expertise in Verification Methodologies like UVM, OVM, VMM
  • Knowledge of ARM based SoC verification / Interface protocols like PCIe, USB, SATA/SOC verification
  • Should have experience in creating test plans
  • Familiarity with scripting languages
  • Good written and communication skills

8) Lead Analog Circuit Design Engineer:

Designation: Analog Design – Sr. Engineer/Lead
Experience: 7+ years
Location: Hyderabad/Bangalore
Qualification: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major

Desired Skills:

  • In depth familiarity with transistor level circuit design – sound CMOS design fundamentals
  • Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc.
  • Aware of ESD issues (ie. circuit techniques, layout)
  • Familiarity with custom digital design (ie. high speed logic paths)
  • Knowledge of design for reliability (ie. EM, IR, aging, etc…)
  • Knowledge of layout effects (ie. matching, reliability, proximity effects, etc…)
  • Familiar with Custom design and/or Cadence, HSPICE, HSIM,Ultrasim,etc
  • Exposure to scripting for post processing of simulation results (ie. TCL, PERL, MATLAB etc…)
  • Some knowledge of system level budgeting (ie. jitter, amplitude, noise, etc…)
  • Aware of signal integrity issues (ie. effects of packaging, board parasitics, crosstalk, noise)
  • Good communication and documentation skills .

Good To Have

  • Must have worked on atleast one of the Block Design with Full Ownership.
  • High Speed DLL, PLL, CDR, ADC,DAC,USB1.1/USB2.0, OTG.
  • SerDes standards for one of the PCIe.X, SATA, CPRI, Fibre Transceiver.
  • Power Management Blocks such as LDO, Buck Boost, Switching Regulator for more than 1A regulated Output Current.
  • Work experience in PHY (PCIE, USB2, USB3) development.

9) Lead Analog Layout Engineer:

Designation: Analog Design – Sr. Engineer/Lead
Experience: 7+ years
Location: Hyderabad/Bangalore
Qualification: B.E/B.Tech or M.E/M.Tech

Desired Skills:

  • Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
  • Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
  • Responsible for on-time delivery of block-level layouts with acceptable quality.
  • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environments.
  • Guide junior team-members in their execution of Sub block-level layouts & review their work
  • Contribute to effective project-management.

Qualification/Requirements

  • Experience in analog/custom layout design in advanced CMOS process.
  • Expertise in Cadence Virtuoso XL/GXL/EXL and Mentor Graphic Calibre DRC/LVS is a must.
  • Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
  • Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, ESD, DFM rules, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
  • Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
  • Ability to understand design constraints and implement high-quality layouts.
  • Excellent command and problem-solving skills in physical verification of custom layout.
  • Multiple Tape out support experience will be an added advantage.
  • Excellent verbal and written communication skills.